> For the complete documentation index, see [llms.txt](https://docs.cubepilot.org/user-guides/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.cubepilot.org/user-guides/~/changes/mvMsnRI8xnoKpbe3XhLK/cubenode/cubenode-specification.md). # CubeNode Specification ## Dual core * 32-bit Arm® Cortex®-M7 core with double precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/2.14 DMIPS /MHz (Dhrystone 2.1), and DSP instructions * 32-bit Arm® 32-bit Cortex®-M4 core with FPU, Adaptive real-time accelerator (ART AcceleratorTM) for internal Flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instruction ## Memories * Up to 2 Mbytes of Flash memory with readwhile-write support * 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain * CRC calculation unit ## Security * ROP,PC-ROP, active tamper, secure firmware upgrade support, Secure access mode ## Communication peripherals * 2 x CANFD * 2 x UARTs/USARTs * 1 x 10/100Mb Ethernet Phy * 1 x SPI * 1 x I2C * 1 x USB * 1 x SDMMC * 3 axis Accelerometer * 3 axis Gyroscope ## Contents **1.Description**\ **2.Functional overview**\ **2.1 Dual Arm® Cortex® cores**\ **2.2 Memory protection unit (MPU)**\ **2.3 Embedded Flash memory**\ **2.4 Boot modes**\ **2.5 Reset and clock controller (RCC)**\ **2.5.1 System reset sources**\ **2.6 General-purpose input/outputs (GPIOs)**\ **2.7 Analog-to-digital converters (ADCs)**\ **2.8 Inter-integrated circuit interface (I2C)**\ **2.9 Universal asynchronous receiver transmitter (UART)**\ **2.10 Controller area network (FDCAN1, FDCAN2)**\ **2.11 USB**\ **2.12 3 axis Accelerometer**\ **2.13 3 axis Gyroscope**\ **2.14 Ethernet interface**\ **3.Pin descriptions** ## 1 Description CubeNode are based on the high-performance Arm® Cortex®-M7 and Cortex®- M4 32-bit RISC cores.The Cortex®-M7 core operates at up to 480 MHz and the Cortex®- M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which supports Arm® single- and double- precision (Cortex®-M7 core) operations and conversions (IEEE 754 compliant), including a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. CubeNode incorporate high-speed embedded memories with a dual-bank Flash memory of 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/O. * **Standard peripherals** \ One I2C\ Two CANFD\ One UART, One USART\ One Ethernet\ One SPI\ One USB\ One SDMMC ## 2 Functional overview ### 2.1 Dual Arm® Cortex® cores The dual-core CubeNode embed two Arm® cores, a Cortex®-M7 and a\ Cortex®-M4 offers optimal performance for real-time applications while the Cortex®-M7 core can execute high-performance tasks in parallel. The two cores belong to separate power domains. This allows designing gradual highpower efficiency solutions in combination with the low-power modes. ### 2.2 Memory protection unit (MPU) The devices feature two memory protection units. Each MPU manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. ### 2.3 Embedded Flash memory The CubeNode embed 2 Mbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: One Flash word (8 words, 32 bytes or 256 bits)\ 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes (4 K Flash memory words) • 128 Kbytes of System Flash memory from which the device can boot\ 2 Kbytes (64 Flash words) of user option bytes for user configuration ### 2.5 Reset and clock controller (RCC) The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate. Cortex®-M4. The #### 2.5.1 System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: Power-on reset (pwr\_por\_rst)\ Brownout reset\ Low level on NRST pin (external reset)\ Independent watchdog 1 (from D1 domain)\ Independent watchdog 2 (from D2 domain)\ Window watchdog 1\ Window watchdog 2\ Software reset\ Low-power mode security reset\ Exit from Standby ### 2.6 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs register reset values in the device reference manual). The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. ### 2.7 Analog-to-digital converters (ADCs) The STM32H757xI devices embed three analog-to-digital converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to a destination location without any software action. In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. ### 2.8 Inter-integrated circuit interface (I2C) CubeNode embed one I2C interface. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * I2C-bus specification and user manual rev. 5 compatibility: \- Slave and Master modes, multimaster capability\ \- Standard-mode (Sm), with a bitrate up to 100 kbit/s\ \- Fast-mode (Fm), with a bitrate up to 400 kbit/s\ \- Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os\ \- 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses\ \- Programmable setup and hold times\ \- Optional clock stretching * System Management Bus (SMBus) specification rev 2.0 compatibility: \- Hardware PEC (Packet Error Checking) generation and verification with ACK control\ \- Address resolution protocol (ARP) support\ \- SMBus alert Power System Management Protocol (PMBus) specification rev 1.1 compatibility Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming.\ \ Wakeup from Stop mode on address match\ \ Programmable analog and digital noise filters\ \ 1-byte buffer with DMA capability ### 2.9 Universal asynchronous receiver transmitter (USART) CubeNode have two embedded universal asynchronou receiver transmitters (UART7 and UART8) ### 2.10 Controller area network (FDCAN1, FDCAN2) The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit. It have the features: * Supports CAN 2.0 and CAN with Flexible Data-Rate (CAN FD) Physical Layer Transceiver Requirements * Optimized for CAN FD at 2, 5 and 8 Mbps Operation: \- Maximum propagation delay: 120 ns \- Loop delay symmetry: -10%/+10% (2 Mbps) * Qualified According to AEC-Q100 Rev. G * Automatic Thermal Shutdown Protection * Detection of Ground Fault: \- Permanent dominant detection on TXD \- Permanent dominant detection on bus * Automatic Thermal Shutdown Protection * Suitable for 12V and 24V Systems ### 2.11 USB The CubeNode embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification. ### 2.12 3 axis Accelerometer The CubeNode includes industry first 20-bits data format support in FIFO for high-data resolution. This FIFO format encapsulates 18- bits of accelerometer data. * User selectable Accelerometer Full-scale range (g): ± 2/4/8/16. ### 2.13 3 axis Gyroscope The CubeNode includes industry first 20-bits data format support in FIFO for high-data resolution. This FIFO format encapsulates 19-bits of gyroscope data. User selectable Gyro Full-scale range (dps): ± 15.6/31.2/62.5/125/250/500/1000/2000. ### 2.14 Ethernet interface The CubeNode include high-performance 10/100 Ethernet transceiver.It have the features: * Compliant with IEEE802.3/802.3u (Fast Ethernet) * Compliant with ISO 802-3/IEEE 802.3 (10BASE-T) * Loop-back modes * Auto-negotiation * Automatic polarity detection and correction * Vendor specific register functions * HP Auto-MDIX support * Integrated power-on reset circuit ## 3.Pin descriptions
Num PinsPin TypePin NameFunctionAddtional Functions
1I/OCAN1_LCAN1_L
2I/OCAN1_HCAN1_H
3I/OPE1UART8_TXEVENTOUT
4I/OPE0UART8_RXEVENTOUT
5I/OPB8I2C1_SCLTIM16_CH1,TIM4_CH3,UART4_RX,EVENTOUT
6I/OPB7I2C1_SDATIM17_CH1N,TIM4_CH2,USART1_RX,EVENTOUT
7I/OPC10SPI3_SCKUSART3_TX,UART4_TX,EVENTOUT
8I/OPC11SPI3_MISOUSART3_RX,UART4_RX,EVENTOUT
9I/OPC12SPI3_MOSIUART5_TX,EVENTOUT
10I/OPA10/PA8SPI3_CSTIM1_CH1,I2C3_SCL,EVENTOUT
11I/OPB14UBLEDOUTTIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT
12NCNC
13PVDD_3V3VDD_3V3
14I/OCAN2_LCAN2_L
15I/OCAN2_HCAN2_H
16I/OPA14SWCLK
17I/OPA13SWDIO
18INRSTNRST
19IBOOT0BOOT0
20I/OPE2GPIO_PE2SPI4_SCK,EVENTOUT
21I/OPE10GPIO_PE10TIM1_CH2N,EVENTOUT
22I/OPE8UART7_TXTIM1_CH1N,EVENTOUT
23I/OPE7UART7_RXEVENTOUT.
24PGNDGND
25I/OPF3ADC3_INP5EVENTOUT
26I/OPF5ADC3_INP4EVENTOUT
27I/OPC3_CADC3_INP1EVENTOUT
28I/OPC2_CADC3_INP0SPI2_MISO,ADC3_INN1,EVENTOUT
29PGNDGND
30I/OPC9TIM8_CH4TIM3_CH4,I2C3_SDA,EVENTOUT
31I/OPC8TIM8_CH3TIM3_CH3,EVENTOUT
32I/OPD15TIM4_CH4EVENTOUT
33I/OPD14TIM4_CH3EVENTOUT
34I/OPD13TIM4_CH2I2C4_SDA,EVENTOUT
35I/OPD12TIM4_CH1I2C4_SCL,EVENTOUT
36PGNDGND
37I/OPF4ADC3_INP9ADC3_INN5,ADC3_INP9,EVENTOUT
38I/OPF14ADC2_INP6I2C4_SCL,ADC2_INN2,ADC2_INP6,EVENTOUT
39I/OPF13ADC2_INP2EVENTOUT
40I/OPC5ADC2_INP8ADC12_INN4,EVENTOUT
41I/OPA7ADC2_INP7TIM3_CH2,TIM1_CH1N,SPI1_MOSI,TIM14_CH1,EVENTOUT
42PGNDGND
43I/OPC7TIM8_CH2USART6_RX,TIM3_CH2,EVENTOUT
44I/OPC6TIM8_CH1USART6_TX,TIM3_CH1,EVENTOUT
45I/OPB1TIM3_CH4TIM1_CH3N,TIM8_CH3N,TIM8_CH3N,EVENTOUT
46I/OPB0TIM3_CH3TIM1_CH2N,TIM8_CH2N,ADC12_INN5,ADC12_INP9,EVENTOUT
47I/OPE6TIM15_CH2SPI4_MOSI,EVENTOUT
48I/OPB4TIM3_CH1SPI1_MISO,EVENTOUT
49PGNDGND
50I/OPA5ADC1_INP19TIM2_CH1,TIM8_CH1N,SPI1_SCK,EVENTOUT
51I/OPA4ADC1_INP18DAC1_OUT1,EVENTOUT
52I/OPC1ADC1_INP11SPI2_MOSI,EVENTOUT
53I/OPC0ADC1_INP10EVENTOUT
54PGNDGND
55I/OPA3TIM5_CH4TIM2_CH4,TIM15_CH2,USART2_RX,ADC12_INP15,EVENTOUT
56I/OPA2TIM5_CH3TIM2_CH3,TIM15_CH1,USART2_TX,ADC12_INP14,EVENTOUT
57I/OPE5TIM15_CH1SPI4_MISO,EVENTOUT
58I/OPB10TIM2_CH3I2C2_SCL,SPI2_SCK,USART3_TX,EVENTOUT
59I/OPB3TIM2_CH2SPI1_SCK,EVENTOUT
60I/OPA15TIM2_CH1EVENTOUT
61PGNDGND
62I/OPF12ADC1_INP6ADC1_INN2,EVENTOUT
63I/OPC4ADC1_INP4EVENTOUT
64I/OPA6ADC1_INP3TIM3_CH1,SPI1_MISO,TIM13_CH1,EVENTOUT
65I/OPF11ADC1_INP2ADC1_INP2,EVENTOUT
66PGNDGND
67I/OPA1TIM5_CH2TIM2_CH2,UART4_RX,ADC1_INN16,ADC1_INP17,EVENTOUT
68I/OPA0TIM5_CH1TIM2_CH1,UART4_TX,ADC1_INP16,EVENTOUT
69I/OPE14TIM1_CH4SPI4_MOSI,EVENTOUT
70I/OPE13TIM1_CH3SPI4_MISO,EVENTOUT
71I/OPE11TIM1_CH2EVENTOUT
72I/OPE9TIM1_CH1EVENTOUT
73PGNDGND
74PGNDGND
75I/OPA12OTG_FS_DPUART4_TX,EVENTOUT
76I/OPA11OTG_FS_DMTIM1_CH4,UART4_RX,EVENTOUT
77PPA9VBUS
78PVDD_5VVDD_5V
79I/OETHERNET_TX-ETHERNET_TX-
80I/OETHERNET_TX+ETHERNET_TX+
81I/OETHERNET_RX-ETHERNET_RX-
82I/OETHERNET_RX+ETHERNET_RX+
83-84PGNDGND
85-95NCNC
96-97PGNDGND
98-100NCNC
101I/OPB15SDMMC2_D1TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,OTG_HS_DP,EVENTOUT
102I/OPB14SDMMC2_D0TIM1_CH2N,TIM12_CH1,TIM8,CH2N,USART1_TX,SPI2_MISO,OTG_HS_DM,EVENTOUT
103-105NCNC
106I/OPB3SDMMC2_D2TIM2_CH2,SPI1_SCK,EVENTOUT
107I/OPB4SDMMC2_D3TIM3_CH1,SPI1_MISO,EVENTOUT
108-109NCNC
110I/OPD6SDMMC2_CKUSART2_RX,EVENTOUT
111I/OPD7SDMMC2_CMDSPI1_MOSI,EVENTOUT
\*If using Ethernet,do not use pin67,pin56,pin41,pin52,pin63,pin40 \*If using SDMMC2,please do not use pin11,pin48,pin59 \*The CubeNode would not have IMU in first batch \*The Pin83-pin111 would not have in the first batch \*Pin85-pin95,pin96-pin100,pin103-105,pin108-109. please do not connect..It is for future use --- # Agent Instructions This documentation is published with GitBook. GitBook is the documentation platform designed so that both humans and AI agents can read, navigate, and reason over technical content effectively. Learn more at gitbook.com. ## Querying This Documentation If you need additional information that is not directly available in this page, you can query the documentation dynamically by asking a question. Perform an HTTP GET request on the current page URL with the `ask` query parameter, and the optional `goal` query parameter: ``` GET https://docs.cubepilot.org/user-guides/~/changes/mvMsnRI8xnoKpbe3XhLK/cubenode/cubenode-specification.md?ask=&goal= ``` `ask` is the immediate question: it should be specific, self-contained, and written in natural language. `goal` is optional and describes the broader end goal you are ultimately trying to accomplish on behalf of the user. GitBook uses it to tailor the answer towards what is most useful for that goal. The response will contain a direct answer to the question and relevant excerpts and sources from the documentation. Use this mechanism when the answer is not explicitly present in the current page, you need clarification or additional context, or you want to retrieve related documentation sections.